The present invention relates to a circuit for generating a power-on reset signal, and more particularly, to a power-on reset circuit for use in a CMOS integrated circuit.
Generally speaking, a power-on reset circuit provides a reset signal for initializing flip-flops, latches, counters, registers and other such internal components of an integrated circuit, when power is applied thereto. The reset signal maintains a first constant voltage for a sufficient time to allow stabilization of the respective components of the circuit, and after a predetermined time, becomes a second constant voltage (i.e., the operating state voltage which is generally the inversion of the first constant voltage) for as long as the power is applied to the circuit.
Such power-on reset circuits are designed in consideration of steady-state power dissipation, chip layout, production costs and the stability of the reset signal. In designing a power-on reset circuit, the steady-state power dissipation should be minimized. Also, to economize the layout of the chip, the use of passive elements (e.g., capacitors and resistors) which occupy a relatively large area, and depletion-mode transistors which add a manufacturing step, should be avoided.
In order to supply a stable reset signal, the reset signal must be delayed to maintain the first constant voltage for a sufficient period of time. In addition, a discharge circuit is used to eliminate distortion of the reset signal due to the false operation of the reset circuit, which might be caused in a fast switching (on/off) of series power supply voltages.
Here, the power-on reset circuit generally uses a resistor or depletion transistor to stably discharge at internal nodes of the circuit. However, if the discharge path of the circuit is formed with a resistor, the resistor value must be in the range of several megaohms, and such large resistance values occupy a large area in the layout of the chip. On the other hand, if a depletion transistor is used, an additional manufacturing step is required in fabricating the chip.
Alternatively, when the discharge path of the above power-on reset circuit is simply formed of a diode, the voltage cannot be fully discharged at the moment when power is turned off, but is delayed for several milliseconds due to the junction leakage current of the diode. This produces a false operation condition in the reset circuit, which occurs when the power supply voltages may for instance be quickly switched on and off.
A known circuit which meets many of the above criteria is described in U.S. Pat. No. 4,746,822 entitled "CMOS Power-on Reset Circuit," issued to Jone Mahoney, et al. on May 24, 1988.
FIG. 1 illustrates a conventional power-on reset circuit for generating a power-on reset signal by using a capacitor and parasitic diode. In the drawing, the circuit is composed of a delay 1 in which a PMOS transistor P1 and NMOS transistor N1 are serially coupled and a capacitor C1 is connected so that the power-on reset signal is delayed when initial power is supplied, a discharger 2 having a parasitic diode D1 as the discharge path, and an initialization buffer 5 for generating the power-on reset (POR) signal. The initialization buffer 5 includes an input inverter 3 and an initializing circuit 4. The input inverter 3 includes a PMOS transistor P2 and an NMOS transistor N2 connected in series. The initializing circuit 4 includes a PMOS transistor P3 and an NMOS transistor N3 connected in series, and a capacitor C2 connected between the gate of transistors P3 and N3 and the power supply voltage V.sub.DD.
In the operation of the conventional circuit of FIG. 1, at the initial state when a power supply voltage V.sub.DD is applied, the voltage V.sub.DD is at 0 V, making the voltage at node A also zero potential (low level), so that transistor N2 is in the "off" state. As power supply voltage V.sub.DD increases, the voltage at node B increases. When the power supply voltage reaches the threshold voltage of transistor N3, transistor N3 is turned on and the reset signal at node C has a low level (0 V). This reset signal is used to initialize the other parts of an integrated circuit.
If the power supply voltage is greater than the sum of the threshold voltages of transistor N1 and transistor P1 of the delay 1, transistors N1 and P1 are both turned on. At this time, with transistors N1 and P1 turned on, an RC time constant created by capacitor C1 and "on" resistance (voltage drop) of transistor P1 causes a sufficient time to pass before node A and the reset signal at node C become a high level to thereby normally operate the other circuits. When the power supply voltage is turned off, the voltage at node A is discharged through parasitic diode D1 and transistor N4 of the discharger.
In the conventional power-on reset circuit, the voltage at node A is discharged to ground potential by the junction leakage current of parasitic diode D2 in accordance with the threshold voltage of transistor N4. However, if the on/off switching time of the power supply voltage is fast (say, tens of microseconds), the junction leakage current of parasitic diode D2 cannot sufficiently guarantee that the voltage at node A will be fully discharged to ground potential. As a result, the desired reset signal cannot be obtained and thus the power-on reset circuit performs a false operation.
FIG. 2 illustrates the waveforms of the reset signal of the conventional power-on reset circuit in fast switching of the power supply voltage. At the initial power-on state, the reset circuit operates normally to output a desired reset signal. However, thereafter, the discharge path cannot perform normally due to the insecure discharge mechanism of parasitic diode D2 of the reset circuit, so that the reset signal is swung with the same pattern as that of the power supply voltage.
In the conventional power-on reset circuit, a resistor is sometimes used to discharge the voltage at node A. In this case, in order to reduce the stand-by current, a resistor of several megaohms is required, which occupies an excessive amount of layout area of the chip and decreases the efficiency of the layout accordingly.